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AT803 PDF预览

AT803

更新时间: 2022-02-26 12:35:53
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POSEICO /
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4页 173K
描述
PHASE CONTROL THYRISTOR

AT803 数据手册

 浏览型号AT803的Datasheet PDF文件第2页浏览型号AT803的Datasheet PDF文件第3页浏览型号AT803的Datasheet PDF文件第4页 
POSEICO SPA  
Via Pillea 42-44, 16153 Genova - ITALY  
Tel. + 39 010 8599400 - Fax + 39 010 8682006  
Sales Office:  
Tel. + 39 010 8599400 - sales@poseico.com  
PHASE CONTROL THYRISTOR  
AT803  
Repetitive voltage up to  
Mean forward current  
Surge current  
1600 V  
1058 A  
15 kA  
FINAL SPECIFICATION  
Feb. 17 - Issue: 5  
Tj  
[°C]  
Symbol  
Characteristic  
Conditions  
Value  
Unit  
BLOCKING  
V RRM  
V RSM  
V DRM  
Repetitive peak reverse voltage  
Non-repetitive peak reverse voltage  
Repetitive peak off-state voltage  
Repetitive peak reverse current  
Repetitive peak off-state current  
125  
125  
125  
125  
125  
1600  
1700  
1600  
50  
V
V
V
I
I
RRM  
DRM  
V=VRRM  
V=VDRM  
mA  
mA  
50  
CONDUCTING  
I
I
I
T (AV)  
T (AV)  
TSM  
Mean forward current  
180° sin, 50 Hz, Th=55°C, double side cooled  
180° sin, 50 Hz, Tc=85°C, double side cooled  
1058  
834  
15  
A
A
Mean forward current  
Surge forward current  
I² t  
Sine wave, 10 ms  
without reverse voltage  
125  
kA  
x 103  
I² t  
1125  
1,50  
A²s  
V
V T  
On-state voltage  
Threshold voltage  
On-state slope resistance  
On-state current =  
1600 A  
25  
V T(TO)  
125  
125  
0,90  
V
r
T
0,340  
mohm  
SWITCHING  
From 75% VDRM up to 1050 A; gate 10V, 5W  
Linear ramp up to 70% of VDRM  
di/dt  
Critical rate of rise of on-state current, min.  
Critical rate of rise of off-state voltage, min.  
Gate controlled delay time, typical  
Circuit commutated turn-off time, typical  
Reverse recovery charge  
125  
125  
25  
200  
500  
1
A/µs  
V/µs  
µs  
dv/dt  
VD=100V; gate source 25V, 10W , tr=.5 µs  
t
t
d
q
dv/dt = 20 V/µs linear up to 75% VDRM  
di/dt = -20 A/µs, I= 700 A  
VR= 50 V  
200  
µs  
Q rr  
125  
µC  
A
I
I
I
rr  
H
L
Peak reverse recovery current  
Holding current, typical  
VD=5V, gate open circuit  
VD=5V, tp=30µs  
25  
25  
300  
700  
mA  
mA  
Latching current, typical  
GATE  
V GT  
Gate trigger voltage  
VD=5V  
25  
25  
3,50  
150  
0,25  
30  
V
mA  
V
I
GT  
Gate trigger current  
VD=5V  
V GD  
Non-trigger gate voltage, min.  
Peak gate voltage (forward)  
Peak gate current  
VD=VDRM  
125  
V FGM  
V
I
FGM  
10  
A
V RGM  
P GM  
P G  
Peak gate voltage (reverse)  
Peak gate power dissipation  
Average gate power dissipation  
5
V
Pulse width 100 µs  
150  
2
W
W
MOUNTING  
R th(j-h)  
R th(c-h)  
T j  
Thermal impedance, DC  
Thermal impedance  
Operating junction temperature  
Mounting force  
Junction to heatsink, double side cooled  
Case to heatsink, double side cooled  
37,0  
°C/kW  
°C/kW  
°C  
7,0  
-30 / 125  
11,8 / 13,2  
300  
F
kN  
Mass  
g
ORDERING INFORMATION : AT803 S 16  
VRRM/100  
standard specification  

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