Datasheet > AT503

AT503

更新时间： 2022-11-25 11:22:56

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POSEICO		/
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描述
PHASE CONTROL THYRISTOR

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数据手册

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AT503 数据手册

POSEICO SPA

Via N. Lorenzi 8, 16152 Genova - ITALY

Tel. ++ 39 010 6556234 - Fax ++ 39 010 6557519

Sales Office:

POSEICO

POSEICO SPA

POwer SEmiconductors Italian COrporation

Tel. ++ 39 010 6556775 - Fax ++ 39 010 6442510

PHASE CONTROL THYRISTOR

AT503

Repetitive voltage up to

Mean on-state current

Surge current

1600 V

445 A

6.4 kA

FINAL SPECIFICATION

gen 03 - ISSUE : 03

Symbol

Characteristic

Conditions

Value

Unit

[°C]

BLOCKING

V RRM

V RSM

V DRM

I RRM

I DRM

Repetitive peak reverse voltage

Non-repetitive peak reverse voltage

Repetitive peak off-state voltage

Repetitive peak reverse current

Repetitive peak off-state current

125

1600

1700

1600

V=VRRM

V=VDRM

CONDUCTING

I T (AV)

I TSM

I² t

Mean on-state current

Surge on-state current

I² t

180° sin, 50 Hz, Th=55°C, double side cooled

180° sin, 50 Hz, Tc=85°C, double side cooled

sine wave, 10 ms

445

355

6.4

205 x1E3

1.45

0.9

A²s

125

without reverse voltage

V T

On-state voltage

On-state current =

800 A

125

V T(TO)

r T

Threshold voltage

On-state slope resistance

125 0.680

mohm

SWITCHING

di/dt

dv/dt

Critical rate of rise of on-state current, min.

Critical rate of rise of off-state voltage, min.

Gate controlled delay time, typical

Circuit commutated turn-off time, typical

Reverse recovery charge

From 75% VDRM up to 500 A, gate 10V 5ohm

Linear ramp up to 70% of VDRM

VD=100V, gate source 10V, 10 ohm , tr=.5 µs

dV/dt = 20 V/µs linear up to 75% VDRM

di/dt=-20 A/µs, I= 330A

VR= 50 V

VD=5V, gate open circuit

VD=5V, tp=30µs

125

200

500

1.6

A/µs

V/µs

µs

µC

200

Q rr

I rr

I H

125

Peak reverse recovery current

Holding current, typical

300

700

I L

Latching current, typical

GATE

V GT

I GT

Gate trigger voltage

Gate trigger current

Non-trigger gate voltage, min.

Peak gate voltage (forward)

Peak gate current

VD=5V

VD=VDRM

125

3.5

200

0.25

V GD

V FGM

FGM

V RGM

P GM

P G

Peak gate voltage (reverse)

Peak gate power dissipation

Average gate power dissipation

Pulse width 100 µs

MOUNTING

R th(j-h)

R th(c-h)

Thermal impedance, DC

Thermal impedance

Junction to heatsink, double side cooled

Case to heatsink, double side cooled

°C/kW

T j

Operating junction temperature

Mounting force

Mass

-30 / 125

4.9 / 5.9

°C

ORDERING INFORMATION : AT503 S 16

VDRM&VRRM/100

standard specification

12 3 4

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