Datasheet > ASM5P23S09A

ASM5P23S09A

更新时间： 2022-12-27 18:04:56

品牌	Logo	应用领域
PULSECORE		/
页数	文件大小	规格书
18页	353K
描述
3.3V ‘SpreadTrak’ Zero Delay Buffer

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ASM5P23S09A 数据手册

ASM5P23S05A

ASM5P23S09A

November 2006

rev 1.5

3.3V ‘SpreadTrak’ Zero Delay Buffer

General Features

out five low-skew clocks.

•

15MHz to 133MHz operating range, compatible

The -1H version of the ASM5P23SXXA operates at up to

133MHz frequency, and has higher drive than the -1

device. All parts have on-chip PLLs that lock to an input

clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad.

with CPU and PCI bus frequencies.

Zero input - output propagation delay.

Multiple low-skew outputs.

•

Output-output skew less than 250pS.

Device-device skew less than 700pS.

•

One input drives 9 outputs, grouped as 4+4+1

(ASM5P23S09A).

One input drives 5 outputs (ASM5P23S05A).

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium^®based systems.

Test Mode to bypass PLL (ASM5P23S09A only,

refer Select Input Decoding Table).

Available in 16-pin, 150-mil SOIC and 4.4 mm

TSSOP packages for ASM5P23S09A and in

8-pin, 150-mil SOIC and 4.4 mm TSSOP

packages for ASM5P23S05A.

The ASM5P23S09A has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. If all the output clocks are

not required, Bank B can be three-stated. The select input

also allows the input clock to be directly applied to the

outputs for chip and system testing purposes.

•

Multiple ASM5P23S09A and ASM5P23S05A devices can

accept the same input clock and distribute it. In this case

the skew between the outputs of the two devices is

guaranteed to be less than 700pS.

•

3.3V operation

Advanced 0.35µ CMOS technology.

‘SpreadTrak’.

All outputs have less than 200 pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 350 pS, and the output to output skew is

guaranteed to be less than 250 pS.

Functional Description

ASM5P23S09A is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks with Spread

Spectrum capability. It is available in a 16-pin package. The

ASM5P23S05A is the eight-pin version of the

ASM5P23S09A. It accepts one reference input and drives

The ASM5P23S09A and the ASM5P23S05A are available

in two different configurations, as shown in the ordering

information table. The ASM5P23SXXA-1 is the base part.

The ASM5P23SXXA-1H is the high drive version of the -1

part and its rise and fall times are much faster than -1 part.

Block Diagram

MUX

PLL

CLKOUT

CLKA1

CLKA2

CLKA3

PLL

REF

CLKOUT

REF

CLK1

CLK2

CLK3

CLK4

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

ASM5P23S09A

ASM5P23S05A

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...18

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与ASM5P23S09A相关器件

型号	品牌	描述	获取价格	数据表
ASM5P23S09A-1-16-SR	ALSC	3.3V SpreadTrak Zero Delay Buffer	获取价格
ASM5P23S09A-1-16-SR	PULSECORE	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,	获取价格
ASM5P23S09A-1-16-ST	ALSC	3.3V SpreadTrak Zero Delay Buffer	获取价格
ASM5P23S09A-1-16-ST	PULSECORE	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,	获取价格
ASM5P23S09A-1-16-TR	ALSC	3.3V SpreadTrak Zero Delay Buffer	获取价格
ASM5P23S09A-1-16-TR	PULSECORE	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,	获取价格

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