Datasheet > ASM5P2304A

ASM5P2304A

更新时间： 2022-12-20 07:46:12

品牌	Logo	应用领域
PULSECORE		/
页数	文件大小	规格书
14页	349K
描述
3.3V Zero Delay Buffer

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ASM5P2304A 数据手册

November 2006

rev 1.5

ASM5P2304A

3.3V Zero Delay Buffer

Features

the REF pin. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250pS, and the output-to-output skew is guaranteed to

be less than 200pS.

•

Zero input - output propagation delay, adjustable

by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P2304A

Configurations Table”.

•

Input frequency range: 15MHz to 133MHz

Multiple low-skew outputs.

The ASM5P2304A has two banks of two outputs each.

Multiple ASM5P2304A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500pS.

•

Output-output skew less than 200pS.

Device-device skew less than 500pS.

Two banks of four outputs.

•

Less than 200pS Cycle-to-Cycle jitter

(-1, -1H, -2, -2H).

Available in space saving, 8 pin 150-mil SOIC

packages.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

The ASM5P2304A is available in two different

configurations (Refer “ASM5P2304A Configurations Table).

The ASM5P2304A-1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The ASM5P2304A-1H is the high-drive

version of the -1 and the rise and fall times on this device

are much faster.

•

Functional Description

The ASM5P2304A-2 allows the user to obtain REF and

1/2X or 2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

ASM5P2304A is

a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks in PC,

workstation, datacom, telecom and other high-performance

applications. It is available in 8 pin package. The part has

an on-chip PLL which locks to an input clock presented on

Block Diagram

FBK

CLKA1

PLL

REF

CLKA2

Extra Divider (-2)

CLKB1

CLKB2

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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ASM5P2304A-1H	ONSEMI	3.3 V Zero Delay Buffer	获取价格