Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Advanced I/O
Features and Benefits
•
•
•
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
•
•
•
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
•
•
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
Reprogrammable Flash Technology
†
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
2.5 V / 5.0 V Input
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
•
•
•
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
‡
Hot-Swappable and Cold Sparing I/Os
High Performance
†
Programmable Output Slew Rate and Drive Strength
•
•
350 MHz System Performance
Weak Pull-Up/-Down
†
3.3 V, 66 MHz 64-Bit PCI
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL†
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard
®
®
(AES) Decryption (except ARM -enabled ProASIC 3 devices)
•
•
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
†
via JTAG (IEEE 1532–compliant)
®
•
FlashLock to Secure FPGA Contents
Low Power
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
•
•
•
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
•
•
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
†
High-Performance Routing Hierarchy
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
•
Segmented, Hierarchical Routing and Clock Structure
•
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
®
•
M1 ProASIC3 Devices—ARM Cortex™-M1 Soft Processor
Available with or without Debug
1
ProASIC3 Devices
Cortex-M1 Devices
System Gates
A3P015
A3P030
A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
2
M1A3P250 M1A3P400
M1A3P600 M1A3P1000
15,000
30,000
60,000 125,000
250,000
400,000
600,000
1,000,000
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
128
384
–
256
768
–
512
1,536
18
4
1,024
3,072
36
2,048
6,144
36
–
9,216
54
–
13,824
108
24
–
24,576
144
32
–
–
8
8
12
FlashROM Kbits
1
1
1
1
1
1
1
1
3
Secure (AES) ISP
–
–
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Yes
1
Integrated PLL in CCCs
–
–
4
VersaNet Globals
6
6
18
2
18
18
18
18
18
I/O Banks
2
2
2
4
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
300
Package Pins
5
QFN
QN68
QN48, QN68,
QN132
QN132
QN132
QN132
CS
CS121
VQ100
TQ144
VQFP
TQFP
PQFP
FBGA
VQ100
VQ100
TQ144
PQ208
VQ100
PQ208
PQ208
PQ208
PQ208
5
FG144
FG144 FG144/256
FG144/256/ FG144/256/ FG144/256/
484
484
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
† A3P015 and A3P030 devices do not support this feature.
‡ Supported only by A3P015 and A3P030 devices.
January 2013
I
© 2013 Microsemi Corporation
5秒后页面跳转
MAX6675资料手册参数详解、引脚配置说明
LM258引脚图及功能介绍、主要参数分析
CD4052资料手册参数详解、引脚配置说明
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
