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9DBU0431 PDF预览

9DBU0431

更新时间: 2023-12-20 18:46:36
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
17页 3455K
描述
4-output 1.5V PCIe Zero-Delay/Fanout Clock Buffer

9DBU0431 数据手册

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4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB  
9DBU0431  
DATASHEET  
Description  
Features/Benefits  
The 9DBU0431 is a member of IDT's 1.5V Ultra-Low-Power  
(ULP) PCIe family. The device has 4 output enables for clock  
management, and 3 selectable SMBus addresses.  
LP-HCSL outputs; save 8 resistors compared to standard  
HCSL outputs  
45mW typical power consumption in PLL mode; eliminates  
thermal concerns  
Recommended Application  
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)  
Spread Spectrum (SS) compatible; allows SS for EMI  
reduction  
OE# pins; support DIF power management  
HCSL-compatible differential input; can be driven by  
common clock sources  
Output Features  
4 – 1-167MHz Low-Power (LP) HCSL DIF pairs  
SMBus-selectable features; optimize signal integrity to  
Key Specifications  
DIF cycle-to-cycle jitter <50ps  
DIF output-to-output skew <50ps  
DIF phase jitter is PCIe Gen1-2-3 compliant  
application  
slew rate for each output  
differential output amplitude  
Pin/software selectable PLL bandwidth and PLL Bypass;  
optimize PLL to application  
DIF bypass mode additive phase jitter is <300fs rms for  
PCIe Gen3  
Outputs blocked until PLL is locked; clean system start-up  
Device contains default configuration; SMBus interface not  
required for device control  
DIF bypass mode additive phase jitter <350fs rms for  
12k-20MHz  
3.3V tolerant SMBus interface works with legacy controllers  
Three selectable SMBus addresses; multiple devices can  
easily share an SMBus segment  
Space saving 32-pin 5x5mm VFQFPN; minimal board  
space  
Block Diagram  
vOE(3:0)#  
4
CLK_IN  
DIF3  
CLK_IN#  
SS-  
Compatible  
PLL  
DIF2  
DIF1  
vSADR  
DIF0  
^vHIBW_BYPM_LOBW#  
CONTROL  
LOGIC  
^CKPWRGD_PD#  
SDATA_3.3  
SCLK_3.3  
9DBU0431 REVISION C 04/22/15  
1

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