Datasheet > 87952AYI

87952AYI

更新时间： 2024-02-01 18:46:43

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
10页	142K
描述
PLL Based Clock Driver, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

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技术参数
数据手册

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87952AYI 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
JESD-30 代码：	S-PQFP-G32	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
端子数量：	32	封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	FLATPACK
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	GULL WING	端子位置：	QUAD
Base Number Matches：	1

87952AYI 数据手册

ICS87952I

LOW SKEW, 1-TO-11

LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS87952I is a low voltage, low skew LVCMOS/

• Fully integrated PLL

,&6

LVTTL Clock Generator and a member of the

• 11 LVCMOS / LVTTL outputs, 7Ω typical output impedance

• LVCMOS / LVTTL REF_CLK input

HiPerClockS™

HiPerClockS™ family of High Performance Clock

Solutions from ICS. With output frequencies up to

180MHz, the ICS87952I is targeted for high

• Output frequency range up to 180MHz at V_DD= 3.3V ± 5%

• VCO range: 240MHz to 480MHz

performance clock applications. Along with a fully integrated PLL,

the ICS87952I contains frequency configurable outputs and an

external feedback input for regenerating clocks with “zero delay”.

• External feedback for “zero delay” clock regeneration

• Cycle-to-cycle jitter: 100ps (typical)

• 3.3V supply voltage

For test and system debug purposes, the nPLL_EN input al-

lows the PLL to be bypassed. When HIGH, the MR/nOE input

resets the internal dividers and forces the outputs to the high

impedance state.

• -40°C to 85°C ambient operating temperature

• Compatible with MPC952

The low impedance LVCMOS/LVTTL outputs of the ICS87952I

are designed to drive terminated transmission lines. The effec-

tive fanout of each output can be doubled by utilizing the ability

of each output to drive two series terminated transmission lines.

BLOCK DIAGRAM

PIN ASSIGNMENT

nPLL_EN

24 23 22 21 20 19 18 17

REF_CLK

FB_IN

÷4/÷6

QA0

VDDO

QB2

V^DDO

PHASE

VCO

240-480MHz

÷2

QA1

QA2

QA3

QA4

DETECTOR

QA2

QB3

QA1

GNDO

QC0

GNDO

QA0

LFP

ICS87952I

VCO_SEL

F_SELA

V^DD

QC1

VDDA

÷4/÷2

QB0

QB1

QB2

QB3

V^DDO

nPLL_EN

F_SELB

32-Lead LQFP

7mm x 7mm x 1.4mm package body

÷2/÷4

QC0

QC1

F_SELC

MR/nOE

Y package

Top View

87952AYI

www.icst.com/products/hiperclocks.html

REV. A APRIL 30, 2003

12 3 4 5 6 7...10

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