Datasheet > 74AUP1G175GW-Q100

74AUP1G175GW-Q100

更新时间： 2024-02-13 22:13:08

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
18页	262K
描述
Low-power D-type flip-flop with reset; positive-edge triggerProduction

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74AUP1G175GW-Q100 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	TSSOP	包装说明：	PLASTIC, SC-88, SOT-363, SOP-6
针数：	6	Reach Compliance Code：	compliant
风险等级：	5.73	Base Number Matches：	1

74AUP1G175GW-Q100 数据手册

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74AUP1G175-Q100

Low-power D-type flip-flop with reset; positive-edge trigger

Rev. 5 — 13 July 2023

Product data sheet

1. General description

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock

(CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time

requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the

Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action

at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very

low static and dynamic power consumption across the entire V_CCrange from 0.8 V to 3.6 V. This

device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry disables

the output, preventing the potentially damaging backflow current through the device when it is

powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 0.8 V to 3.6 V

CMOS low power dissipation

High noise immunity

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial Power-down mode operation

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

12 3 4 5 6 7...18

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