生命周期: | Obsolete | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.65 |
Is Samacsys: | N | 系列: | AC |
JESD-30 代码: | R-PDIP-T16 | 逻辑集成电路类型: | XOR GATE |
功能数量: | 4 | 输入次数: | 2 |
端子数量: | 16 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
传播延迟(tpd): | 8.2 ns | 认证状态: | Not Qualified |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 3 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子形式: | THROUGH-HOLE | 端子位置: | DUAL |
Base Number Matches: | 1 |
型号 | 品牌 | 描述 | 获取价格 | 数据表 |
74AC11086NE4 | TI | Quadruple 2-Input Exclusive-OR Gates 16-PDIP -40 to 85 |
获取价格 |
|
74AC11109 | TI | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
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|
74AC11109D | TI | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85 |
获取价格 |
|
74AC11109DR | TI | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85 |
获取价格 |
|
74AC11109D-T | PHILIPS | J-K Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO16 |
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|
74AC11112 | TI | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
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