生命周期: | Transferred | 包装说明: | , |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.58 | Is Samacsys: | N |
其他特性: | RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY | 系列: | ACT |
JESD-30 代码: | R-CDFP-F14 | JESD-609代码: | e4 |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | D FLIP-FLOP |
位数: | 1 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 输出极性: | COMPLEMENTARY |
封装主体材料: | CERAMIC, METAL-SEALED COFIRED | 封装形状: | RECTANGULAR |
封装形式: | FLATPACK | 传播延迟(tpd): | 20 ns |
认证状态: | Not Qualified | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | MILITARY | 端子面层: | GOLD |
端子形式: | FLAT | 端子位置: | DUAL |
总剂量: | 300k Rad(Si) V | 触发器类型: | POSITIVE EDGE |
最小 fmax: | 76 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 描述 | 获取价格 | 数据表 |
5962F9671401VEC | INTERSIL | Radiation Hardened Dual J-K Flip-Flop |
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5962F9671401VEX | RENESAS | ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SBDI |
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5962F9671401VXC | INTERSIL | Radiation Hardened Dual J-K Flip-Flop |
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5962F9671401VXX | RENESAS | ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC28 |
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5962F9671402V9A | RENESAS | ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-1 |
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5962F9671402VEC | ETC | J-K-Type Flip-Flop |
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