54FCT273FM

更新时间： 2024-02-08 05:13:57

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
8页	148K
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54FCT273FM 数据手册

August 1998

54FCT273

Octal D-Type Flip-Flop

General Description

Features

n Eight edge-triggered D flip-flops

n Buffered common clock

The ’FCT273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

n Buffered, asynchronous Master Reset

n See ’FCT377 for clock enable version

n See ’FCT373 for transparent latch version

n See ’FCT374 for TRI-STATE^®version

n Output sink capability of 32 mA, source capability of

12 mA

n TTL input and output level compatible

n CMOS power consumption

n Standard Microcircuit Drawing (SMD) 5962-8765601

The register is fully edge-triggered. The state of each D in-

put, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The de-

vice is useful for applications where the true output only is re-

quired and the Clock and Master Reset are common to all

storage elements.

Ordering Code

Military

Package

Number

Package Description

54FCT273DMQB

54FCT273FMQB

54FCT273LMQB

J20A

20-Lead Ceramic Dual-In-Line

20-Lead Cerpack

W20A

E20A

20-Lead Ceramic Leadless Chip Carrier, Type C

Connection Diagrams

Pin Assignment for DIP

and Flatpack

Pin Assignment

for LCC

DS100956-2

DS100956-1

Names

D₀–D₇

Description

Data Inputs

Master Reset

(Active LOW)

Clock Pulse Input

(Active Rising Edge)

Data Outputs

Q₀–Q₇

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100956

www.national.com

12 3 4 5 6 7 8

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