54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A – JANUARY 1991 – REVISED APRIL 1996
54ACT16657 . . . WD PACKAGE
74ACT16657 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
1T/R
1OE
NC
1ERR
GND
1A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1ODD/EVEN
1PARITY
GND
1B1
1B2
2
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
3
CC
4
5
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
6
1A2
V
7
V
CC
CC
500-mA Typical Latch-Up Immunity at
125°C
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
9
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
description
The ’ACT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
V
V
CC
CC
2B7
2B8
GND
2PARITY
2ODD/EVEN
2T/R
2A7
2A8
GND
2ERR
NC
2OE
Odd or even parity is selected by a logic high or
low level, respectively, on the 1ODD/EVEN (or
2ODD/EVEN) input. 1PARITY (or 2PARITY)
carries the parity bit value; it is an output from the
parity generator/checker in the transmit mode and
an input to the parity generator/checker in the
receive mode.
NC – No internal connection
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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