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3N191_TO-78 PDF预览

3N191_TO-78

更新时间: 2022-09-18 23:31:35
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描述
a monolithic dual enhancement mode P-Channel Mosfet

3N191_TO-78 数据手册

  
3N191  
P-CHANNEL MOSFET  
The 3N191 is a monolithic dual enhancement mode P-Channel Mosfet  
FEATURES  
The 3N191 is a dual enhancement mode P-Channel  
Mosfet and is ideal for space constrained applications  
and those requiring tight electrical matching.  
DIRECT REPLACEMENT FOR INTERSIL 3N191  
LOW GATE LEAKAGE CURRENT  
LOW TRANSFER CAPACITANCE  
IGSS ± 10pA  
Crss 1.0pF  
ABSOLUTE MAXIMUM RATINGS1@ 25°C (unless otherwise noted)  
The hermetically sealed TO-78 package is well suited  
for high reliability and harsh environment applications.  
Maximum Temperatures  
Storage Temperature  
65°C to +150°C  
55°C to +135°C  
(See Packaging Information).  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation (one side)  
Continuous Power Dissipation (one side)  
MAXIMUM CURRENT  
300mW  
525mW  
3N191 Features:  
Drain to Source2  
50mA  
ƒ
ƒ
ƒ
Very high Input Impedance  
High Gate Breakdown Voltage  
Low Capacitance  
MAXIMUM VOLTAGES  
Drain to Gate or Drain to Source2  
Transient Gate to Source2,3  
GateGate Voltage  
30V  
±125V  
±80V  
3N191 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVDSS  
BVSDS  
VGS  
CHARACTERISTIC  
MIN  
40  
40  
3.0  
2.0  
2.0  
‐‐  
‐‐  
‐‐  
‐‐  
5.0  
‐‐  
TYP.  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
MAX  
‐‐  
‐‐  
UNITS  
V
CONDITIONS  
Drain to Source Breakdown Voltage  
Source to Drain Breakdown Voltage  
Gate to Source Voltage  
ID = 10µA  
IS = 10µA, VBD = 0V  
VDS = 15V, ID = 500µA  
VDS = 15V, ID = 500µA  
VDS = VGS , ID = 10µA  
VGS = 40V  
6.5  
5.0  
5.0  
10  
10  
200  
400  
30  
300  
4000  
VGS(th)  
Gate to Source Threshold Voltage  
IGSSR  
IGSSF  
IDSS  
Gate Reverse Leakage Current  
Forward Gate Leakage Current  
Drain to Source Leakage Current  
Source to Drain Leakage Current  
Drain Current “On”  
VGS = 40V  
VDS = 15V  
VSD = 15V VDB = 0  
pA  
ISDS  
ID(on)  
rDS(on)  
gfs  
mA  
Ω
µS  
VDS = 15V, VGS = 10V  
VDS = 20V, ID = 100µA  
VDS = 15V, ID = 5mA , f = 1kHz  
Drain to Source “On” Resistance  
Forward Transconductance4  
1500  
Yos  
Output Admittance  
‐‐  
‐‐  
300  
Click To Buy  
Ciss  
Crss  
Coss  
Input Capacitance  
Reverse Transfer Capacitance  
Output Capacitance  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
4.5  
1.0  
3.0  
pF  
VDS = 15V, ID = 5mA , f = 1MHz  
MATCHING CHARACTERISTICS 3N191  
SYMBOL  
LIMITS  
CHARACTERISTIC  
Forward Transconductance Ratio  
UNITS  
ns  
mV  
CONDITIONS  
VDS = 15V, ID = 500µA , f = kHz  
VDS = 15V, ID = 500µA  
MIN  
0.85  
‐‐  
MAX  
1.0  
100  
gfs1/gfs2  
VGS12  
Gate Source Threshold Voltage  
Differential5  
VGS12/T  
Gate Source Threshold Voltage  
Differential Change with Temperature5  
VDS = 15V, ID = 500µA, TS = 55°C to +25°C  
VDS = 15V, ID = 500µA, TS = +25°C to +125°C  
‐‐  
100  
µV/°C  
SWITCHING CHARACTERISTICS  
SYMBOL  
td(on)  
tr  
CHARACTERISTIC  
MIN  
‐‐  
‐‐  
TYP  
‐‐  
‐‐  
MAX  
15  
30  
UNITS  
ns  
CONDITIONS  
Turn On Delay Time  
Turn On Rise Time  
Turn Off Time  
VDD = 15V, ID(on) = 5mA, RG = RL = 1.4KΩ  
toff  
‐‐  
‐‐  
50  
Note 1 Absolute maximum ratings are limiting values above which 3N191 serviceability may be impaired.  
Note 2 – Per Transistor  
Note 3 – Approximately doubles for every 10°C in TA  
Note 4 – Measured at end points, TA and TB  
Note 5 – Pulse: t= 300µS, Duty Cycle 3%  
Device Schematic  
TO-78 (Bottom View)  
Available Packages:  
3N191 in TO-72  
3N191 in bare die.  
Tel: +44 1603 788967  
Email: chipcomponents@micross.com  
Web: http://www.micross.com/distribution  
Please contact Micross for full  
package and die dimensions  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  

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