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3D7424-1 PDF预览

3D7424-1

更新时间: 2024-02-19 18:46:38
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
6页 363K
描述
MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

3D7424-1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
系列:7424输入频率最大值(fmax):16 MHz
JESD-30 代码:R-PDIP-T14长度:19.305 mm
逻辑集成电路类型:ACTIVE DELAY LINE功能数量:1
抽头/阶步数:4端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
可编程延迟线:YES认证状态:Not Qualified
座面最大高度:4.58 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):21 ns
宽度:7.62 mmBase Number Matches:1

3D7424-1 数据手册

 浏览型号3D7424-1的Datasheet PDF文件第2页浏览型号3D7424-1的Datasheet PDF文件第3页浏览型号3D7424-1的Datasheet PDF文件第4页浏览型号3D7424-1的Datasheet PDF文件第5页浏览型号3D7424-1的Datasheet PDF文件第6页 
3D7424  
MONOLITHIC QUAD 4-BIT  
PROGRAMMABLE DELAY LINE  
(SERIES 3D7424)  
FEATURES  
PACKAGES  
Four indep’t programmable lines on a single chip  
I1  
SC  
I2  
I3  
I4  
1
2
3
4
5
6
7
14  
VDD  
All-silicon CMOS technology  
13  
12  
11  
10  
9
AL  
Low quiescent current (5mA typical)  
O1  
SO  
O2  
O3  
O4  
Leading- and trailing-edge accuracy  
I1  
SC  
I2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
AL  
Vapor phase, IR and wave solderable  
O1  
SO  
O2  
O3  
O4  
I3  
Increment range: 0.75ns through 400ns  
Delay tolerance: 3% or 2ns (see Table 1)  
Line-to-line matching: 1% or 1ns typical  
Temperature stability: ±1.5% typical (-40C to 85C)  
Vdd stability: ±0.5% typical (4.75V to 5.25V)  
Minimum input pulse width: 10% of total delay  
SI  
GND  
I4  
SI  
8
GND  
8
SOIC-14  
DIP-14  
3D7424D-xx  
3D7424-xx  
For mechanical dimensions, click here.  
For package marking details, click here.  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The 3D7424 device is a small, versatile, quad 4-bit programmable  
monolithic delay line. Delay values, programmed via the serial interface,  
can be independently varied over 15 equal steps. The step size (in ns) is  
determined by the device dash number. Each input is reproduced at the  
corresponding output without inversion, shifted in time as per user  
selection. For each line, the delay time is given by:  
I1-I4  
Signal Inputs  
O1-O4 Signal Outputs  
AL  
SC  
SI  
Address Latch In  
Serial Clock In  
Serial Data In  
SO  
Serial Data Out  
VDD 5.0V  
TDn = T0 + An * TI  
GND Ground  
where T0 is the inherent delay, An is the delay address of the n-th line  
and TI is the delay increment (dash number). The desired addresses are  
shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The  
serial interface can also be used to enable/disable each delay line. The 3D7424 operates at 5 volts and  
has a typical T0 of 6ns. The 3D7424 is TTL/CMOS-compatible, capable of sourcing or sinking 4mA loads,  
and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-  
insertable DIP and a space saving surface mount 14-pin SOIC.  
TABLE 1: PART NUMBER SPECIFICATIONS  
DELAYS & TOLERANCES (NS)  
INPUT RESTRICTIONS  
Part  
Delay  
Step  
Inherent  
Total  
Relative  
Max Frequency  
Min Pulse Width  
Number  
Delay  
Delay  
Tolerance  
Recom’d Absolute Recom’d  
Absolute  
3D7424-.75  
3D7424-1  
3D7424-1.5  
3D7424-2  
3D7424-4  
3D7424-5  
3D7424-10  
3D7424-15  
3D7424-20  
3D7424-40  
3D7424-50  
3D7424-100  
3D7424-200  
3D7424-400  
3% or 0.50ns  
3% or 0.50ns  
3% or 0.50ns  
3% or 0.75ns  
3% or 0.75ns  
3% or 0.75ns  
3% or 1.25ns  
3% or 1.88ns  
3% or 2.50ns  
3% or 5.00ns  
3% or 6.25ns  
3% or 12.5ns  
3% or 25.0ns  
3% or 50.0ns  
19 MHz  
16 MHz  
12 MHz  
9.2 MHz  
5.0 MHz  
4.1 MHz  
2.1 MHz  
1.4 MHz  
1.0 MHz  
550 KHz  
440 KHz  
220 KHz  
110 KHz  
55 KHz  
166 MHz  
166 MHz  
111 MHz  
83 MHz  
83 MHz  
66 MHz  
33 MHz  
22 MHz  
16 MHz  
8.3 MHz  
6.6 MHz  
3.3 MHz  
1.6 MHz  
833 KHz  
26 ns  
32 ns  
3.0 ns  
.75 ± 0.19 6.0 ± 2.0 17.25 ± 2.0  
3.0 ns  
1.0 ± 0.25 6.0 ± 2.0  
1.5 ± 0.38 6.0 ± 2.0  
2.0 ± 0.50 6.0 ± 2.0  
4.0 ± 1.00 6.0 ± 2.0  
5.0 ± 1.25 6.0 ± 2.0  
10 ± 2.50 6.0 ± 2.0  
15 ± 3.75 6.0 ± 2.0  
20 ± 5.00 6.0 ± 2.0  
40 ± 10.0 6.0 ± 2.0  
50 ± 10.0 6.0 ± 2.0  
100 ± 12.5 6.0 ± 2.0  
21.0 ± 2.0  
28.5 ± 2.0  
36.0 ± 2.0  
66.0 ± 2.0  
81.0 ± 2.5  
156 ± 5.0  
231 ± 7.5  
306 ± 10  
606 ± 20  
756 ± 25  
1506 ± 50  
43 ns  
4.5 ns  
54 ns  
99 ns  
6.0 ns  
6.0 ns  
122 ns  
234 ns  
347 ns  
459 ns  
909 ns  
1.2 us  
2.3 us  
4.5 us  
9.0 us  
7.5 ns  
15.0 ns  
22.5 ns  
30.0 ns  
60.0 ns  
75.0 ns  
150 ns  
300 ns  
600 ns  
200 ± 20.0 6.0 ± 2.0 3006 ± 100  
400 ± 40.0 6.0 ± 2.0 6006 ± 200  
NOTE: Any increment between 0.75ns and 400ns not shown is also available as standard  
See page 4 for details regarding input restrictions  
2006 Data Delay Devices  
Doc #06019  
6/5/2006  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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